Input/output line structure of a semiconductor memory device

ABSTRACT

A semiconductor memory device including a plurality of memory blocks, and a plurality of input/output lines associated with the memory blocks, is disclosed. The input/output lines are divided into at least a first group and a second group. A first parts of the input/output lines of the first group are arranged between adjacent memory blocks while first parts of the input/output lines of the second group are arranged on circuit blocks around the adjacent memory blocks, and second parts of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second parts of the input/output lines of the second group are arranged between the adjacent memory blocks.

[0001] This application relies for priority upon Korean Patent Application No. 2000-00940, filed on Jan. 10, 2000, the contents of which are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

[0002] The present invention relates to a semiconductor memory device, and more particularly to an arrangement of input/output lines and circuit associated with sense amplifiers in a semiconductor memory device.

BACKGROUND OF THE INVENTION

[0003] A general arrangement of a semiconductor memory device, as shown in FIG. 1, is figured out by a divided memory banks and peripheral circuit. Assuming that the semiconductor memory device formed on semiconductor chip 1 has a storage capacity of 128 Mb, each of four banks BANK1-BANK4 is 32 Mb. The peripheral circuit disposed between the memory banks at the center of the chip 1 includes circuits for decoding, buffering, and data input/output.

[0004] In constructing the memory bank of 32 Mb, as shown in FIG. 2, row decoder 20 and column decoder 30 are positioned the sides of the memory bank, and 8 K (K is 210) wordlines and 4 K bitline pairs are arranged in a matrix form. The memory array of 32 Mb in the memory bank is hierarchically divided in 16 memory blocks 40 (or MB0˜MB15) along a row direction, each memory block having a storage capacity of 2 Mb with 512 wordlines and 4 K bitlines. 1 K (1024) column selection lines CSLO˜CSL1023 lead from the column decoder 30 are arranged on and over the memory array, each corresponding four bitlines. When a refresh cycle is assigned to 4 K, two wordlines per one memory bank are activated. For example, the row decoder 20 selects one memory block (e.g., MB1) among the memory blocks MB0˜MB7 and one memory block (e.g., MB9) among the memory blocks MB8˜MB15, and then selects one wordline in each of the selected memory blocks MB1 and MB9. Namely, two wordlines are selected when one memory bank is selected, and other memory blocks in the selected memory bank are non-selected.

[0005] The encircled part A in FIG. 2, including the memory block MB1 and the around, is shown in FIG. 3. Between adjacent memory blocks, a sense amplifier block is positioned. For instance, sense amplifier blocks SABLK0 and SABLK1 are interposed between the memory blocks MB0 and MB1, and between the memory blocks MB1 and MB2, respectively. The sense amplifier block is composed of bitline isolation regions 50 and 60, bitline precharging/equalizing region 70, P-channel sense amplifier region 80, N-channel sense amplifier region 90, and input/output gating region 100. See U.S. Pat. No. 5,761,123 entitled “Sense amplifier circuit of a nonvolatile semiconductor memory device”, relevant to circuit elements provided to the bitline isolation regions, the precharging/equalizing region, and the sense amplifier regions.

[0006] In the input/output gating region 100, four pairs of input/output lines, IOi,/IOi, IOj,/IOj, IOk,/IOk, IOl, and/IOl, are arranged with being perpendicular to the bitlines, and column selection gates GT are connected between bitline pairs and input/output line pairs. When a row of the memory block MB1 is selected by the row decoder 20 and a column selection line (e.g., CSL0) is selected by the column decoder 30, bitline pair BL0 and/BL0 is connected to the input/output line pair IOi and/IOi located on the left side of MB1, through the corresponding column selection gate pair whose gates are coupled to CSL0. Also, BL2 and/BL2 are connected to IOj and/IOj arranged at the left side of MB1, through their corresponding column selection gates whose gates are coupled to CSL0. At the same time, BL1 and/BL1 are connected to IOi and/IOi arranged at the right side of MB1, and BL3 and/BL3 are connected to IOj and/IOj arranged at the right side of MB1, through their corresponding column selection gates whose gates are coupled to CSL0. Thus, one of the column selection lines can connect four bitline pairs to four input/output line pairs alternately arranged on the both side of the memory block MB1. As mentioned above, as two wordlines are activated upon the selection of MB1, data of four bits for one wordline is transferred to four input/output line pairs. As a result, eight bits are read out from one selected memory bank, which means such a memory device is operable with 8-bit data structure.

[0007] If two column selection lines (e.g., CSL0 and CSL512) are selected at the same time, 8-bit data is read out from the selected memory block MB1 by the sense amplifier block corresponding thereto. In more detail, when CSL0 is selected, four bitline pairs BL0,/BL0, BL1,/BL1, BL2,/BL2, BL3, and/BL3 are connected to their corresponding input/output lines IOi,/IOi, IOj, and/IOj. In the same manner, the bitline pairs of BL2048 and /BL2048, and of BL2050 and/BL2050, are connected to the input/output line pairs of IOk and/IOk, and of IOl and/IOl, respectively, the input/output line pairs being arranged at the left side of MB1, through their corresponding column selection gate GT whose gates are coupled to CSL512. While, the bitline pairs of BL2049 and/BL2049, and of BL2051/BL2051, are connected to the input/output line pairs of IOk and/IOk, and of IO and/IOl, respectively, the input/output line pairs being arranged at the right side of MB1, through their corresponding column selection gate GT whose gates are coupled to CSL512.

[0008] Therefore, it can be seen from FIG. 3 that eight bitline pairs are each connected to eight input/output line pairs alternately arranged at the both side of the selected memory block MB1 when two column selection lines (e.g., CSL0 and CSL512) are activated at the same time. Since two wordlines are selected in one memory bank, one wordline being activated each in one memory block out of two selected memory block, the activation with two column selection signals enables 16-bit data to be read out of the selected memory banks.

[0009] It is possible to make an alternation between the 8-bit and 16-bit data read-out pattern in the array architecture shown in FIG. 3, and further available to construct 4-bit data structure by multiplexing the input/output line pairs with additional column address bits. Other bitlines and selection gates involved in the activation of other column selection lines are operationally arranged in the same configuration as described above. Referring to FIG. 4 showing a layout pattern of the circuit arrangement of FIG. 3, gate lines 102 made of polysilicon layers are formed over N+ active regions 101. The bitlines and active regions 101 are connected at contact region 11, and the active regions and input/output lines made of a metal or conductive material are connected at contact region 13.

[0010] The width of the input/output gating region, L, is determined by an integration density dependent upon the number of input/output lines disposed therein. On the gating region interposed between the adjacent memory blocks, eight input/output lines are arranged to provide an efficient data access operation, alternately positioned at the both sides of a memory block. However, it is well understood that a chip size of a memory device is forced to be smaller in accordance with minimized electronic apparatuses employing the memory device. Therefore, the topological density of a memory device is more increased and mostly influenced from repetitive patterns of the signal lines such as bitlines, or input/output lines as the memory device goes to a larger capacity and a more integration. In view of the horizontal arrangement with the input/output lines, there are inoperable areas without contacts to the active regions, just being arranged over the active regions and bitlines, and causing the width L to be extended.

SUMMARY OF THE INVENTION

[0011] It is therefore an object of the present invention to provide an efficient input/output line arrangement that is advantageous in reducing a topological size of a semiconductor memory device.

[0012] It is another object of the invention to provide an optimized input/output line structure of a semiconductor memory device, reducing a circuit area occupied by a repetitive arrangement with the input/output lines.

[0013] In order to attain the above objects, a semiconductor memory device includes a plurality of memory blocks, and a plurality of input/output lines associated with the memory blocks, the input/output lines being divided into at least a first group and a second group. A first parts of the input/output lines of the first group are arranged between adjacent memory blocks while first parts of the input/output lines of the second group are arranged on circuit blocks around the adjacent memory blocks, and second parts of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second parts of the input/output lines of the second group are arranged between the adjacent memory blocks.

[0014] The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more complete appreciation of the present invention, and many of the attendant advantages thereof, will become readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:

[0016]FIG. 1 is a schematic view of a general arrangement in a semiconductor memory device;

[0017]FIG. 2 is a schematic view of a detail inter-arrangement within a memory bank of the device shown in FIG. 1;

[0018]FIG. 3 is an internal circuit view of the encircled part in FIG. 2, disclosing a conventional construction with an input/output gating region;

[0019]FIG. 4 is a top view showing a layout pattern over the input/output gating region of FIG. 3;

[0020]FIG. 5 is an internal circuit view of the encircled part in FIG. 2, disclosing an advanced construction with an input/output gating region according to the present invention; and

[0021]FIGS. 6A through 6C are top views showing embodied layout patterns over the input/output gating region of FIG. 5.

[0022] The prefix “/” attached to reference numerals for lines (bitlines or input/ouput lines) means the complementary of the corresponding matter.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0023] It should be understood that the description of this preferred embodiment is merely illustrative and that it should not be taken in a limiting sense. In the following detailed description, several specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details.

[0024] The embodiment of the invention is applied to a high density dynamic random access memory (DRAM) and available to data structures of 16-bit as well as 8-bit. FIG. 5 shows an arrangement with input/output lines between memory blocks, including the bitline isolation blocks 50 and 60, the bitline precharging/equalizing blocks 70, and the sense amplifier blocks 80 and 90. The structural feature of FIG. 5 is symmetrically aligned into the left and right sides of a memory block (e.g., MB1), and also into the upper and lower arrays of interface region 200 so that the blocks, 60 through 90, and the memory blocks are divided into two portions (upper and lower portions).

[0025] The input/output lines are allocated in the gating region between the sense amplifier blocks 80 and 90, by two pairs. The i'th pair of IOi and /IOi, and the j'th pair of IOj and/IOj, hereinafter referred to as “the first input/output line group”, are disposed between the upper sense amplifier blocks associated to the upper memory blocks, and positioned in the lower sense amplifier blocks associated to the lower memory blocks. In the upper array UA, gates of four column selection transistors GT correspondingly connected to the two input/output line pairs of the i'th and the j'th are coupled to CSL0 in common so as to connect the i'th and j'th input/output line pairs to bitline pairs of the bitline pairs BLO's (BL0 and/BL0) through BL2048's (BL2047 and/BL2047). Each column selection transistor connects one input/output line to one bitline. The upper array UA is assigned to 512 column selection lines CSL0˜CSL511.

[0026] By the contrary, in the lower array LA, the k'th pair of IOk and/IOk, and the l'th pair of IOl and/IOl, hereinafter referred to as “the second input/output line group”, are disposed between the lower sense amplifier blocks associated to the lower memory blocks, and positioned in the upper sense amplifier blocks associated to the upper memory blocks. The interconnection manner with the column selection lines and transistors GT is identical to that in the upper array LA, connecting the k'th and l'th input/output line pairs to bitline pairs of the bitline pairs BL2048's (BL2048 and/BL2048) through BL4095's (BL4095 and/BL4095). The lower array LA includes also 512 column selection lines CSL512˜CSL1023.

[0027] The first and second input/output line groups are aligned to a same column axis in order not to need a further volume along a row direction, which can reduce the width (shown in FIG. 4) of the input/output gating region.

[0028] When a wordline in a memory block (e.g., MB1) and one column selection line (e.g., CSL0) are selected, the first bitline pair of BL0 and/BL0 is connected to the input/output line pair of IOi and/IOi arranged at the left side of the selected memory block MB1 through its column selection transistors GT, and the third bitline pair of BL2 and/BL2 is connected to the input/output line pair of IOj and/IOj arranged at the left side of the selected memory block MB1 through its corresponding column selection transistors GT. At the same time, BL1 and/BL1 are connected to IOi and/IOi arranged at the right side of the selected memory block MB1, and BL3 and /BL3 are connected to IOj and/IOj arranged at the right side of MB1. Thus, one column selection line makes four pairs of bitlines be connected to four pairs of input/output lines alternately arranged at the both sides of the selected memory block MB1. As two wordlines each for two memory blocks are activated in one memory bank, one wordline per one memory block, 4-bit data is each transferred to the four input/output line pairs arranged at the both sides of each of the two memory blocks. Thus, 8-bit data is read out from a selected memory bank, the memory device being operable in 8-bit data structure.

[0029] When two column selection lines (e.g., CSL0 and CSL512) are simultaneously activated, 8-bit data is turned out of the selected memory block MB1 by means of the sense amplifier block. Responding to an activation of CSL0, four pairs of bitlines, BL0 and/BL0, BL1 and/BL1, BL2 and/BL2, and BL3 and/BL3, are connected to their corresponding input/output line pairs, IOi and/IOi, IOj and/IOj, IOk and/IOk, and IOl and /IOl, alternately arranged at the both sides of MB1, through the column selection transistors GT whose gates are coupled to CSL0. And, responding to an activation of CSL512, four pairs of bitlines, BL2048 and/BL2048, BL2049 and/BL2049, BL2050 and/BL2050, and BL2051 and/BL2051, are connected to their corresponding input/output line pairs, IOi and/IOi, IOj and/IOj, IOk and/IOk, and IOl and/IOl, alternately arranged at the both sides of MB1, through the column selection transistors GT whose gates are coupled to CSL512. As 8-bit data is read out from one memory bank and two wordlines each for two memory blocks are activated, 16-bit data is read out of the selected memory blocks (e.g., MB1 and MB9), the memory device being operable in 16-bit data structure.

[0030]FIGS. 6A through 6C shows available layout patterns according to the arrangement with the input/output lines, which makes it possible to certify a reduced width of the input/output gating region. The input/output lines are made of the first metal layers. Throughout FIGS. 6A through 6C, the first input/output line group of IOi,/IOi, IOj, and/IOj is disposed between the sense amplifier blocks 80 and 90 in the upper array UA, and arranged on the sense amplifier blocks 80 and 90 while in the lower array LA. The second input/output line group of IOk,/IOk, IOl, and/IOl is disposed between the sense amplifier blocks 80 and 90 in the lower array LA. It can be understood, in FIG. 6A, that he other part of the second input/output group not shown is arranged on the sense amplifier blocks 80 and 90 in the adjacent array as the first group is done in the lower array LA. Thus, the width of the input/output gating region, L′, is reduced more than the conventional one L shown in FIG. 4. It can be seen that, approximately, the present L′ may be a half of the conventional L.

[0031] While the interface region 200 a in FIG. 6A acts as a boundary defining the upper and lower arrays, or a passage zone where the input/output lines changes their arrangement features, the interface regions 200 b and 200 c each in FIGS. 6B and 6C provide spaces for connecting the input/output lines separately arranged in the upper and lower arrays for themselves. Each of the input/output lines , IOi˜IOl, is interconnected therewith in the interface region through contact regions 15 and the second metal layers 17.

[0032] That is, referring to FIG. 6B, a part of IOi arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of IOi arranged on the sense amplifier block 90 in the lower array LA. A part of IOj arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of IOj arranged on the sense amplifier block 90 in the lower array LA. A part of/IOi arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of/IOi arranged on the sense amplifier block 80 in the lower array LA. And, a part of/IOj arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of/IOj arranged on the sense amplifier block 80 in the lower array LA.

[0033] In FIG. 6C, an entire alternation with the first and second input/output line groups is disclosed over the upper and lower arrays, including interface region 200 c where the self-interconnections of the input/output lines themselves are made by the contact regions 15 and the second metal layers 17. A part of IOi arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of IOi arranged on the sense amplifier block 90 in the lower array LA. A part of IOj arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of IOj arranged on the sense amplifier block 90 in the lower array LA. A part of/IOi arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of/IOi arranged on the sense amplifier block 80 in the lower array LA. And, a part of/IOj arranged between the sense amplifier blocks 80 and 90 in the upper array UA is connected to the other part of/IOj arranged on the sense amplifier block 80 in the lower array LA.

[0034] A part of IOk arranged between the sense amplifier blocks 80 and 90 in the lower array LA is connected to the other part of IOk arranged on the sense amplifier block 90 in the upper array UA. A part of IOl arranged between the sense amplifier blocks 80 and 90 in the lower array LA is connected to the other part of IOl arranged on the sense amplifier block 90 in the upper array UA. A part of/IOk arranged between the sense amplifier blocks 80 and 90 in the lower array LA is connected to the other part of/IOk arranged on the sense amplifier block 80 in the upper array UA. And, a part of/IOl arranged between the sense amplifier blocks 80 and 90 in the lower array LA is connected to the other part of/IOl arranged on the sense amplifier block 80 in the upper array UA. Different from the interconnection features of the first group, the second group utilizes additional layers of the first metal to connect their upper and lower parts. Such additional metal layers in the interface region 200 c are optional components to adaptively adjust the arrangement topology in the gating region.

[0035] As described above, since the width of the input/output gating region where repetitive patterns of input/output lines cause the layout density is reduced at least by a half of the conventional matters, a layout margin is larger and an overall chip size would be smaller than before.

[0036] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as described in the accompanying claims. Although, in the embodiment, the parts of the input/output lines are arranged on the sense amplifier blocks, it would be understood by those skilled in the art that it is available to set the arrangement position of the parts in other admittable regions around their corresponding memory blocks. 

What is claimed is:
 1. A semiconductor memory device: a plurality of memory blocks; a plurality of input/output lines associated with the memory blocks; wherein the input/output lines are divided into at least a first group and a second group; wherein first parts of the input/output lines of the first group are arranged between adjacent memory blocks while first parts of the input/output lines of the second group are arranged on circuit blocks around the adjacent memory blocks, and second parts of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second parts of the input/output lines of the second group are arranged between the adjacent memory blocks. 